The present invention relates generally to microelectronic circuits, and more particularly to trench MOSFET devices.
A DMOS (Double diffused MOS) transistor is a type of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) that uses diffusion to form the transistor region. DMOS transistors are typically employed as power transistors for high voltage power integrated circuits. DMOS transistors provide high current per unit area where low forward voltage drops are required.
A typical discrete DMOS circuit includes two or more individual DMOS transistor cells which are fabricated in parallel. The individual DMOS transistor cells share a common drain contact, while their sources are all shorted together with metal and their gates are shorted together by polysilicon. Thus, even though the discrete DMOS circuit is constructed from a matrix of smaller transistors, it behaves as if it were a single large transistor.
One particular type of DMOS transistor is a so-called trench DMOS transistor in which the channel is formed vertically and the gate is formed in a trench extending between the source and drain. The trench, which is lined with a thin oxide layer and filled with polysilicon, allows less constricted current flow and thereby provides lower values of specific on-resistance. Examples of trench DMOS transistors are disclosed in U.S. Pat. Nos. 5,072,266, 5,541,425, and 5,866,931.
FIG. 1 illustrates half of a hexagonally shaped prior art trench DMOS structure 21. The structure includes an n+ substrate 23, upon which is grown a lightly doped epitaxial layer (n) 25 of a predetermined depth depi. Within the epi layer 25, a body region 27 of opposite conductivity (p, p+) is provided. Except in a central region, the p body region is substantially planar and lies a distance dmin below the top surface of the epi layer. Another layer 28 (n+) overlying most of the body region 27 serves as source. A hexagonally shaped trench 29 is provided in the epitaxial layer, opening toward the top and having a predetermined depth dtr. The trench 29 is associated with a transistor cell defines a cell region 31 that is also hexagonally shaped in horizontal cross-section. Within the cell region 31, the body region rises to the top surface of the epi layer and forms an exposed pattern 33 in a horizontal cross section at the top surface of the cell region. This central exposed portion of the body region is more heavily doped (p+) than the substantially planar remainder of the body region. Further, this central portion of the body region extends to a depth dmax below the surface of the epi layer that is greater than the trench depth dtr for the transistor cell. A central portion 27c of the body region lies below a plane that is defined by the bottom of the trench 29 for the transistor cell. By creating such a deep p+ region, breakdown voltage is forced away from the trench surface and into the bulk of the semiconductor material.
Demand persists for trench DMOS devices having ever-lower on-resistance. The simplest way to reduce on-resistance is to increase cell density. Unfortunately, with a device such as that shown in FIG. 1, the cell density is limited by lateral diffusion of dopant in the p+ region. More specifically, as the dimensions of the trench mesa region are reduced to increase cell density, the p+ region eventually diffuses laterally into the channel region, significantly increasing the threshold voltage of the device.
It is also well known that the gate charges associated with trench DMOS devices increase when cell density is increased, for example, in connection with efforts to lower on-resistance. One way to combat such an increase in gate charge is to reduce the depth of the trenches and the corresponding P-body junction depth. By reducing trench depth (and the associated P-body junction depth), gate charge can be decreased. Unfortunately, when trench depth and P-body junction depth are decreased, device breakdown voltage degrades in the termination area due to the shallower P-body junction in this area.
Hence, efforts to provide low on-resistance in trench DMOS devices by increasing cell density are presently frustrated by detrimental changes that simultaneously occur, for example, in connection with device threshold voltage, gate charge, and/or termination-area device breakdown voltage.
The above and other obstacles in the prior art are addressed by the MOSFET devices of the present invention.
According to an embodiment of the invention, a trench MOSFET device is provided, which comprises:
(a) a substrate of a first conductivity type;
(b) an epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate;
(c) a plurality of trenches within the epitaxial layer;
(d) a first insulating layer, such as an oxide layer, lining the trenches;
(e) a conductive region, such as a polycrystalline silicon region, within the trenches adjacent to the first insulating layer;
(f) one or more trench body regions and one or more termination body regions provided within an upper portion of the epitaxial layer, the termination body regions extending into the epitaxial layer to a greater depth than the trench body regions; each trench body region and each termination body region comprising (1) a first region of a second conductivity type, the second conductivity type being opposite the first conductivity type, and (2) a second region of the second conductivity type adjacent the first region, the second region having a greater majority carrier concentration than the first region, and the second region being disposed above the first region; and
(g) a plurality of source regions of the first conductivity type positioned adjacent the trenches within upper portions the trench body regions.
In some preferred embodiments, the trench MOSFET device is a silicon device having a specific on-resistance ranging from 0.13 to 0.22 ohm-cm2 and a breakdown voltage ranging from 20 to 30 V.
In others, the termination body regions preferably range from 2.0 to 2.2 xcexcm in minimum depth and the trench body regions preferably range from 1.6 to 1.8 xcexcm in maximum depth. The trench body regions preferably range from 1.2 to 2.0 xcexcm in maximum width and the trenches preferably range from 1.0 to 2.0 xcexcm in maximum depth.
In some preferred embodiments, the device will further comprise a terminal masking feature, such as a terminal oxide feature, spaced at least 3.0 microns from an adjacent peripheral trench.
In other preferred embodiments, the first conductivity type is N-type conductivity, the second conductivity type is P-type conductivity, and the body regions are doped with boron. More preferably, the substrate is an N+ substrate, the epitaxial layer is an N epitaxial layer, the first region is a Pxe2x88x92 region, the second region is a P region, and the source regions are N+ regions.
Several preferred resistivity values for the trench MOSFET of the present invention are as follows:
a substrate resistivity ranging from 0.005 to 0.01 ohm-cm,
an epitaxial layer resistivity ranging from 0.18 to 0.25 ohm-cm,
a first region resistivity ranging from 0.4 to 0.8 ohm-cm,
a second region resistivity ranging from 0.15 to 0.4 ohm-cm, and
source region resistivities ranging from 0.003 to 0.001 ohm-cm.
Such values are particularly preferred in connection with 20 to 30 V devices.
According to another aspect of the invention, a method of forming a trench MOSFET device is provided. The method comprises:
(a) providing a substrate of a first conductivity type;
(b) forming an epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate;
(c) forming a plurality of trenches within the epitaxial layer, the trenches being lined by a first insulating layer and containing a conductive region adjacent to the first insulating layer;
(d) forming within an upper portion of the epitaxial layer one or more trench body regions and one or more termination body regions, the termination body regions extending into the epitaxial layer to a greater depth than the trench body regions; each trench body region and each termination body region comprising (a) a first region of a second conductivity type, the second conductivity type being opposite the first conductivity type, and (b) a second region of the second conductivity type adjacent the first region, the second region having a greater majority carrier concentration than the first region, and the second region being disposed above the first region; and
(e) forming a plurality of source regions of the first conductivity type adjacent the trenches within upper portions the trench body regions.
The first insulating layer is preferably an oxide layer, and the step of forming the oxide layer preferably comprises dry oxidation.
The step of forming the trenches preferably includes the step of forming a patterned masking layer over the epitaxial layer and etching the trenches through the masking layer.
The step of providing a conductive region within the trenches preferably comprises depositing a layer of polycrystalline silicon and subsequently etching the polycrystalline silicon.
The step of forming the one or more trench body regions and the one or more termination body regions preferably comprises: (a) forming a terminal masking feature; (b) forming a layer of second conductivity type within an upper portion of the epitaxial layer; (c) forming the trenches in the epitaxial layer, the trenches extending through the layer of second conductivity type such that distinct first regions of second conductivity type are formed; (d) forming an oxide layer over at least portions of trench walls adjacent the first regions, the step of forming the oxide layer resulting in areas of reduced majority carrier concentration within the first regions adjacent the oxide layer; and (e) forming second regions of second conductivity type within the epitaxial layer adjacent to and above the first regions of second conductivity type. The trenches are preferably spaced sufficiently close such that, during the step of forming the oxide layer, the majority concentration is reduced throughout the first regions between the trenches. The terminal masking feature is preferably spaced sufficiently far from a nearest peripheral trench such that the step of forming the oxide layer has substantially no effect on bulk majority carrier concentration in the first regions between the peripheral trench and the masking feature.
Preferably, the maximum distance between the trenches ranges from 1.2 to 2.0 microns and the minimum distance between the peripheral trenches and the terminal oxide feature ranges from 3.0 to 4.0 microns.
The step of forming the layer of second conductivity type and the step of forming the second regions preferably includes implanting and diffusing a dopant into the epitaxial layer.
In one preferred instance, the step forming the oxide layer over at least portions of the trench walls adjacent the first regions comprises dry oxidation at a temperature ranging from 900 to 1100xc2x0 C., more preferably 900 to 950xc2x0 C. In another instance, this step comprises oxidation in steam at a temperature ranging from 900 to 1100xc2x0 C., more preferably 900 to 950xc2x0 C.
Preferably, the step of forming the source regions comprises forming a patterned masking layer and implanting and diffusing a dopant into upper portions of the trench body regions.
One advantage of the present invention is that a trench MOSFET device with increased cell density, and hence lower on-resistance, is provided without a substantial increase in device threshold voltage.
Other advantages of the present invention are that such a trench MOSFET device can be provided without a substantial increase in gate charge and without a substantial degradation in device breakdown voltage in the termination areas.
Yet another advantage of the present invention is that a trench MOSFET device is provided with increased cell density, decreased trench depth and decreased P-body junction depth, while avoiding a substantial degradation of device breakdown voltage in the termination areas. Moreover, breakdown in the termination areas is prevented without resorting to additional steps to deepen the Pxe2x88x92 type region in the termination area.
These and other embodiments and advantages of the present invention will become immediately apparent to those of ordinary skill in the art upon review of the Detailed Description and claims to follow.